? semiconductor components industries, llc, 2012 september, 2012 ? rev. 2 1 publication order number: ncp336/d ncp336, ncp337 3 a ultra-small controlled load switch with auto-discharge path description the ncp336 and ncp337 are very low ron mosfet controlled by external logic pin, allowing optimization of battery life, and portable device autonomy. indeed, thanks to a current consumption optimization with pmos structure, leakage currents are eliminated by isolating connected ic on the battery when not used. output discharge path is also embedded to eliminate residual voltages on the output rail for the ncp337 part only. proposed in a wide input voltage range from 1.2 v to 5.5 v, in a small 1 x 1.5 mm wlcsp6, pitch 0.5 mm. features ? 1.2 v ? 5.5 v operating range ? 21 m p mosfet at 4.5 v ? dc current up to 3 a ? output auto ? discharge ? active high en pin ? wlcsp6 1 x 1.5 mm ? this device is pb ? free, halogen free/bfr free and is rohs compliant applications ? mobile phones ? tablets ? digital cameras ? gps ? portable devices figure 1. typical application circuit eny enx ncp336 or ncp337 in a2 in b2 gnd c1 en c2 out b1 out a1 smps dcdc converter vcc 0 platform ic?n v+ ls platform ic?n+1 ls or ldo 100n 1 f http://onsemi.com wlcsp6 fc suffix case 567fh pin connections (top view) see detailed ordering and shipping information on page 8 of this data sheet. ordering information out out gnd in in en 2 1 a b c
ncp336, ncp337 http://onsemi.com 2 table 1. pin function description pin name pin number type description in a2, b2 power load ? switch input voltage; connect a 1 f or greater ceramic capacitor from in to gnd as close as possible to the ic. gnd c1 power ground connection. en c2 input enable input, logic high turns on power switch. out a1, b1 output load ? switch output; connect a 1 f ceramic capacitor from out to gnd as close as possible to the ic is recommended. figure 2. block diagram
ncp336, ncp337 http://onsemi.com 3 table 2. maximum ratings rating symbol value unit in, out, en, pins: (note 1) v en, v in, v out ? 0.3 to + 7.0 v from in to out pins: input/output (note 1) v in, v out 0 to + 7.0 v maximum junction temperature t j ? 40 to + 125 c storage temperature range t stg ? 40 to + 150 c moisture sensitivity (note 2) msl level 1 stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. table 3. operating conditions symbol parameter conditions min typ max unit v in operational power supply 1.2 5.5 v v en enable voltage 0 5.5 t a ambient temperature range ? 40 25 +85 c t j junction temperature range ? 40 25 +125 c c in decoupling input capacitor 1 f c out decoupling output capacitor 1 f r ja thermal resistance junction to air wlcsp package (note 3) 100 c/w i out maximum dc current 3 a p d power dissipation rating (note 4) t a 25 c wlcsp package 0.66 w t a = 85 c wlcsp package 0.26 w 1. according to jedec standard jesd22 ? a108. 2. moisture sensitivity level (msl): 1 per ipc/jedec standard: j ? std ? 020. 3. the r ja is dependent of the pcb heat dissipation and thermal via. 4. the maximum power dissipation ( pd ) is given by the following formula: p d t jmax t a r ja
ncp336, ncp337 http://onsemi.com 4 table 4. electrical characteristic min & max limits apply for t a between ? 40 c to +85 c for v in between 1.2 v to 5.5 v (unless otherwise noted). typical values are referenced to t a = +25 c and v in = 5 v (unless otherwise noted). symbol parameter conditions min typ max unit power switch r dson static drain ? source on ? state resistance vin = 5.5 v i = 1 a (note 5) 20 22 m vin = 4.5 v i = 500 ma (note 5) 21 25 vin = 3.3 v i = 500 ma (note 5) 23 28 vin = 2.5 v i = 500 ma (note 5) 28 35 vin = 1.8 v i = 250 ma (note 5) 40 45 vin = 1.2 v t a = 25 c, i = 200 ma 95 120 rdis output discharge path en = low 70 90 v ih high ? level input voltage 0.9 v v il low ? level input voltage 0.5 r pd en pull down resistor 5 m quiescent current istd standby current vin = 4.2 v en = low, no load 1 a iq quiescent current vin = 4.2 v en = high, no load 1 a timings t en enable time vin = 3.6 v (note 6) r l = 25 , cout = 1 f 323 s t r output rise time r l = 25 , cout = 1 f 810 t on on time (t en + t r ) r l = 25 , cout = 1 f 1130 t f output fall time ncp337. r l = 25 , cout = 1 f 42 5. guaranteed by design and characterization 6. parameters are guaranteed for c load and r load connected to the out pin with respect to the ground timings figure 3. enable, rise and fall time t f vout en vin t dis t off t r t en t on
ncp336, ncp337 http://onsemi.com 5 typical characteristics figure 4. rdson (m ) vs. vin (v) figure 5. rdson (m ) vs. iload (a) figure 6. rdson (m ) vs. temperature ( c) at 100 ma figure 7. rdson (m ) vs. temperature ( c) at 3 a
ncp336, ncp337 http://onsemi.com 6 typical characteristics figure 8. standby ( a) and leakage current ( a) vs. vin (v) figure 9. standby current ( a) vs. temperature ( c) figure 10. leakage current ( a) vs. temperature ( c) figure 11. quiescent current ( a) vs. temperature ( c)
ncp336, ncp337 http://onsemi.com 7 figure 12. enable time and rise time figure 13. disable time and fall time functional description overview the ncp337 is a high side p channel mosfet power distribution switch designed to isolate ics connected on the battery in order to save energy. the part can be turned on, with a wide range of battery from 1.2 v to 5.5 v. enable input enable pin is an active high. the path is opened when en pin is tied low (disable), forcing p mos switch off. the in/out path is activated with a minimum of vin of 1.2 v and en forced to high level. auto discharge nmos fet is placed between the output pin and gnd, in order to discharge the application capacitor connected on out pin. the auto ? discharge is activated when en pin is set to low level (disable state). the discharge path (pull down nmos) stays activated as long as en pin is set at low level and vin > 1.2 v. in order to limit the current across the internal discharge nmosfet, the typical value is set at 70 . cin and cout capacitors in and out, 1 f, at least, capacitors must be placed as close as possible the part to for stability improvement.
ncp336, ncp337 http://onsemi.com 8 application information power dissipation main contributor in term of junction temperature is the power dissipation of the power mosfet. assuming this, the power dissipation and the junction temperature in normal mode can be calculated with the following equations: ? p d = r ds(on) x (i out ) 2 p d = power dissipation (w) r ds(on) = power mosfet on resistance ( ) i out = output current (a) ? t j = p d x r ja + t a t j = junction temperature ( c) r ja = package thermal resistance ( c/w) t a = ambient temperature ( c) pcb recommendations the ncp337 integrates an up to 3 a rated pmos fet, and the pcb design rules must be respected to properly evacuate the heat out of the silicon. by increasing pcb area, especially around in and out pins, the r ja of the package can be decreased, allowing higher power dissipation. figure 14. routing example: 2 oz, 4 layers with vias across 2 internal inners. example of application definition. t j t a r ja p d r ja r ds(on) i 2 t j : junction temperature. t a : ambient temperature. r = thermal resistance between ic and air, through pcb. r ds(on) : intrinsic resistance of the ic mosfet. i: load dc current. taking into account of r obtain with: ? 1 oz, 2 layers: 100 c/w. at 3 a, 25 c ambient temperature, r ds(on) 20 m @ vin 5 v, the junction temperature will be: t j t a r p d 25 (0.024 3 2 ) 100 43 o c taking into account of r obtain with: ? 2 oz, 4 layers: 60 c/w. at 3 a, 65 c ambient temperature, r ds(on) 24 m @ vin 5 v, the junction temperature will be: t j t a r p d 65 (0.024 3 2 ) 60 78 o c ordering information device marking option package shipping ? ncp337fct2g ac auto discharge wlcsp 1 x 1.5 mm 3000 tape / reel NCP336FCT2G af without autodischarge wlcsp 1 x 1.5 mm 3000 tape / reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp336, ncp337 http://onsemi.com 9 package dimensions wlcsp6, 1.00x1.50 case 567fh issue o seating plane 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to spherical crowns of solder balls. 2x dim a min max 0.54 millimeters a1 d 1.00 bsc e b 0.29 0.34 e 0.50 bsc 0.63 d e a b pin a1 reference ed a 0.05 b c 0.03 c 0.05 c 6x b 123 c b a 0.05 c a a1 a2 c 0.22 0.28 1.50 bsc 0.50 0.25 6x dimensions: millimeters *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.05 c 2x top view side view bottom view note 3 ee a2 0.33 ref recommended a1 package outline ed/2 pitch 0.50 pitch on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncp336/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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